The invention relates to a modulo-2-adder for the logic-linking of three input signals.
Modulo-2-adders are frequently used in the data control of data words where test bits are attached to the data word. The test bits are generated by the binary addition of the data bits. The number of test bits attached to a data word depends upon whether errors are simply to be recognized or also corrected.
In the simplest example the test bits are discovered by the modulo-2-addition of two binary digits. The logic element capable of performing this addition is referred to as a EXCLUSIVE-OR-gate or in brief an EXOR-gate. If more than two data digits are to be binary-added, the adders are connected in the form of a so-called binary tree. An example is shown in FIG. 1 which indicates how eight input signals E1 to E8 are binary-added to form an output signal D. Adders AD1 are arranged at each of the intersection points. For n data bits, thus for n input signals, n-1 adders are required and therefore the binary tree has a depth of m stages, where 2.sup.m =n. The time required to form the result is calculated from the addition time of a binary adder multiplied by the depth of the binary tree. For example, a test bit generator for eight data bits E1 to E8 requires seven adders AD1 which have formed the result D after three addition times.
If adders capable of adding three input signals or three data bits were used to calculate the test bits, a ternary tree corresponding to FIG. 2 would result. Here for n data bits INT(n/2) adders are required and the ternary tree has a depth of m stages, where 3.sup.m =n. If, in accordance with FIG. 2, eight data bits or input signals are to be logic-linked, four three-value adders AD2 are required which have formed the result D after two addition times. If only eight of the nine existing inputs shown in FIG. 2 are used, the remaining input can be used to switch-over between even/odd parity formation.
Ternary trees corresponding to FIG. 2 thus have advantages in relation to binary trees are shown in FIG. 1. To permit these advantages to be exploited in practice, the three-value adders must fulfill two conditions: on the one hand their addition time must not be very much longer than that of the two-value adders, and on the other hand the outlay in respect of the transistors--and thus the space requirement on the chip-must not be very much greater than in the binary adders.